Spi Dma Start Address Register (Iispi) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers
Table A-30. SPIDMAC Register Bits (Cont'd)
Bit(s) Name
11 SPIMME
13:12 SPISx
14 SPIERRS
15 SPIDMAS
16 SPICHS
31:17 Reserved

SPI DMA Start Address Register (IISPI)

The SPI DMA Start Address (
reset value for this register is undefined. This SPI register is a 19-bit
read/write register that contains the start address of the buffer in memory.
SPI DMA Address Modifier Register (IMSPI)
The SPI DMA Address Modifier (
reset value for this register is undefined. This SPI register is a 16-bit
read/write register that contains the address modifier.
A-106
Function
SPI Multimaster Error. Set when MME is
set in the SPISTAT register and DMA is
enabled.
DMA FIFO Status 0. Indicates the status
of the DMA FIFO as follows:
00 = FIFO empty
11 = FIFO full
10 = FIFO partially full
01 = Reserved
DMA Error Status. Set if any of the fol-
lowing error bits get set: SPIOVF,
SPIUNF, or SPIMME
DMA Transfer Status. Indicates the status
of the DMA transfer as follows:
1 = DMA in progress, 0 = DMA idle
DMA Chain Loading Status. Indicates the
status of the DMA chain loading as fol-
lows:
1 = DMA chain pointer loading in prog-
ress, 0 = Chain idle
) register's address is 0x1080. The
IISPI
IMSPI
ADSP-2126x SHARC Processor Hardware Reference
Type
Status
Status
Status
Status
Status
) register's address is 0x1081. The
Default
0
0
0
0