Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 807

Memory blocks and banks. The DSP's internal memory is divided into
blocks that are each associated with different data address generators. The
DSP's external memory spaces is divided into banks, which may be
addressed by either data address generator.
Modified addressing. The DAG generates an address that is incremented
by a value or a register.
Modify address. The Data Address Generator (DAG) increments the
stored address without performing a data move.
Modify registers. A modify register is a Data Address Generator (DAG)
register that provides the increment or step size by which an index register
is pre- or post-modified during a register move.
Multichannel Mode. In this mode, each data word of the serial bit stream
occupies a separate channel.
Multifunction computations. Using the many parallel data paths within
its computational units, the DSP supports parallel execution of multiple
computational instructions. These instructions complete in a single cycle,
and they combine parallel operation of the multiplier and the ALU or dual
ALU functions. The multiple operations perform the same as if they were
in corresponding single-function computations.
Multiplier. This part of a processing element does floating-point and
fixed-point multiplication and executes fixed-point multiply/add and
multiply/subtract operations.
Nonzero numbers. Nonzero, finite numbers are divided into two classes:
normalized and denormalized
ADSP-2126x SHARC Processor Core Manual G-7