Dai Interrupt Controller Registers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Table A-53. DAI_PIN_STAT Register (Cont'd)
Bits Name
6 DAI_P07
7 DAI_P08
8 DAI_P09
9 DAI_P10
10 DAI_P11
11 DAI_P12
12 DAI_P13
13 DAI_P14
14 DAI_P15
15 DAI_P16
16 DAI_P17
17 DAI_P18
18 DAI_P19
19 DAI_P20
31–20 Reserved

DAI Interrupt Controller Registers

The DAI contains its own Interrupt Controller that indicates to the core
when DAI audio peripheral related events occur. Since audio events gener-
ally occur infrequently relative to the SHARC processor core, the DAI
Interrupt Controller reduces all of its interrupts onto two interrupt signals
within the core's primary interrupt systems—one mapped with low prior-
ity and one mapped with high priority. This architecture allows the user
to indicate priority broadly. In this way, the DAI interrupt controller reg-
isters provide 32 independently configurable interrupts labeled
DAI_INT[31:0]
ADSP-2126x SHARC Processor Hardware Reference
Description
Provides status of DAI_P07 pin
Provides status of DAI_P08 pin
Provides status of DAI_P09 pin
Provides status of DAI_P10 pin
Provides status of DAI_P11 pin
Provides status of DAI_P12 pin
Provides status of DAI_P13 pin
Provides status of DAI_P14 pin
Provides status of DAI_P15 pin
Provides status of DAI_P16 pin
Provides status of DAI_P17 pin
Provides status of DAI_P18 pin
Provides status of DAI_P19 pin
Provides status of DAI_P20 pin
, respectively.
Registers Reference
A-167