Analog Devices ADSP-21267 SHARC Manuals

Manuals and User Guides for Analog Devices ADSP-21267 SHARC. We have 1 Analog Devices ADSP-21267 SHARC manual available for free PDF download: Hardware Reference Manual

Analog Devices ADSP-21267 SHARC Hardware Reference Manual

Analog Devices ADSP-21267 SHARC Hardware Reference Manual (846 pages)

Brand: Analog Devices | Category: Computer Hardware | Size: 11 MB

Table of Contents

Hardware Reference
1
Table of Contents
3
Preface

31
- Purpose of this Manual
  31
- Intended Audience
  31
- Manual Contents
  32
- What's New in this Manual
  34
- Technical Support
  34
- Supported Processors
  35
- Product Information
  35
  - Analog Devices Web Site
    36
  - Engineerzone
    36
- Notation Conventions
  37
- Register Diagram Conventions
  38
Introduction

41
- Design Advantages
  41
- Architectural Overview
  44
  - Processor Core
    45
    
    Processing Elements
    45
    
    Program Sequence Control
    46
    
    Processor Internal Buses
    49
  - Processor Peripherals
    50
    
    Dual-Ported Internal Memory (SRAM)
    50
    
    I/O Processor
    51
    
    Digital Audio Interface (DAI)
    53
- Development Tools
  53
- Differences from Previous Sharcs
  54
Processing Elements

59
- Numeric Formats
  61
- Setting Computational Modes
  70
- Using Computational Status
  74
- Arithmetic Logic Unit (ALU)
  75
  - ALU Operation
    75
  - ALU Saturation
    76
  - ALU Status Flags
    77
  - ALU Instruction Summary
    78
- Multiply Accumulator (Multiplier)
  81
- Barrel Shifter (Shifter)
  88
  - Shifter Operation
    89
  - Shifter Status Flags
    93
  - Shifter Instruction Summary
    94
- Data Register File
  96
- Alternate (Secondary) Data Registers
  98
- Multifunction Computations
  99
- Secondary Processing Element (Pey)
  103
  - Dual Compute Units Sets
    105
  - Dual Register Files
    107
  - Dual Alternate Registers
    108
  - SIMD and Status Flags
    108
  - SIMD (Computational) Operations
    108
Program Sequencer

113
- Instruction Pipeline
  116
- Instruction Cache
  117
  - Bus Conflicts
    117
  - Block Conflicts
    119
  - Using the Cache
    120
  - Optimizing Cache Usage
    121
- Branches and Sequencing
  123
  - Conditional Branches
    124
  - Delayed Branches
    125
- Loop and Status Stacks and Sequencing
  128
- Conditional Sequencing
  129
- Core Stalls
  133
  - Execution Stalls
    135
  - DAG Stalls
    136
  - Memory Stalls
    136
  - IOP Register Stalls
    136
  - DMA Stalls
    136
- Loops and Sequencing
  137
  - Restrictions on Ending Loops
    139
  - Restrictions on Short Loops
    140
  - Loop Address Stack
    143
  - Loop Counter Stack
    144
    
    Reading from LCNTR in a LOOP
    148
- SIMD Mode and Sequencing
  148
- Timer and Sequencing
  158
- Interrupts and Sequencing
  160
  - Delayed Interrupt Processing
    164
  - Sensing Interrupts
    165
  - Masking Interrupts
    166
  - Latching Interrupts
    167
  - Stacking Status During Interrupts
    168
  - Nesting Interrupts
    170
  - Reusing Interrupts
    172
  - Interrupting IDLE
    173
- Summary
  173
Data Address Generators

179
- Setting DAG Modes
  182
  - Circular Buffering Mode
    183
  - Broadcast Loading Mode
    183
  - Alternate (Secondary) DAG Registers
    184
  - Bit-Reverse Addressing Mode
    186
- Using DAG Status
  187
- DAG Operations
  187
  - Addressing with Dags
    188
  - Data Addressing Stalls
    190
  - Addressing Circular Buffers
    190
  - Modifying DAG Registers
    195
  - Addressing in SISD and SIMD Modes
    196
- Dags, Registers, and Memory
  197
  - DAG Register-To-Bus Alignment
    197
  - DAG Register Transfer Restrictions
    199
- DAG Instruction Summary
  201
Memory

205
Jtag Test Emulation Port

281
- JTAG Test Access Port
  281
- Boundary Scan
  282
- Background Telemetry Channel (BTC)
  284
- User-Definable Breakpoint Interrupts
  284
  - Restrictions
    285
  - Cycle Count Functionality (EMUCLK) Register
    285
  - Silicon Revision ID
    285
- JTAG Related Registers
  285
  - Instruction Register
    286
  - Enhanced Emulation Status (EEMUSTAT) Register
    288
- Boundary Register
  288
- Built-In Self-Test Operation (BIST)
  289
- Private Instructions
  289
- References
  289
I/O Processor

292
- General Procedure for Configuring DMA
  292
- Iop/Core Interaction Options
  293
  - Interrupt-Driven I/O
    293
  - Polling/Status Driven I/O
    297
  - DMA Controller Operation
    298
    
    Chaining DMA Processes
    300
- Address Register
  302
- Setting up DMA Parameter Registers
  311
  - DMA Transfer Direction
    311
  - Data Buffer Registers
    313
  - Port, Buffer, and DMA Control Registers
    314
  - Addressing
    316
  - Setting up DMA
    320
Parallel Port

323
- Parallel Port Pins
  325
  - Alternate Pin Functions
    326
    
    Parallel Ports as FLAG Pins
    326
    
    Parallel Data Acquisition Port as Address Pins
    327
- Parallel Port Operation
  327
  - Basic Parallel Port External Transaction
    327
  - Reading from an External Device or Memory
    328
  - Writing to an External Device or Memory
    329
  - Transfer Protocol
    330
    
    8-Bit Mode
    331
  - Comparison of 16-Bit and 8-Bit SRAM Modes
    333
- Parallel Port Interrupt
  334
- Parallel Port Throughput
  334
  - 8-Bit Access
    336
  - Conclusion
    337
  - Parallel Port Registers
    337
  - Parallel Port DMA Registers
    338
  - Parallel Port External Setup Registers
    339
- Using the Parallel Port
  339
  - DMA Transfers
    340
  - Core Driven Transfers
    340
    
    Known Duration Accesses
    342
    
    Interrupt Driven Accesses
    344
    
    Status Driven Transfers (Polling)
    344
- Parallel Port Programming Examples
  345
Serial Ports

351
- Serial Port Signals
  355
- SPORT Operation Modes
  359
  - Standard DSP Serial Mode
    361
    
    Standard DSP Serial Mode Control Bits
    361
    
    Data Formatting
    362
    
    Frame Sync Options
    362
    
    Data Transfers
    363
    
    Status Information
    363
  - Left-Justified Sample Pair Mode
    364
    
    Left-Justified Sample Pair Mode Control Bits
    365
    
    Setting the Internal Serial Clock and Frame Sync Rates
    365
    
    Setting Word Length (SLEN)
    365
    
    Enabling SPORT Master Mode (MSTR)
    366
    
    Selecting Transmit and Receive Channel Order (FRFS)
    366
- Selecting Frame Sync Options (DIFS)
  366
- Enabling SPORT DMA (SDEN)
  367
  - Interrupt-Driven Data Transfer Mode
    367
  - DMA-Driven Data Transfer Mode
    367
- I 2 S Mode
  368
- Multichannel Operation
  374
  - Frame Syncs in Multichannel Mode
    376
    
    Active State Multichannel Receive Frame Sync Select
    377
  - Multichannel Mode Control Bits
    377
    
    Active State Transmit Data Valid
    379
    
    Multichannel Status Bits
    379
    
    Receive Multichannel Frame Sync Source
    379
    
    Channel Selection Registers
    380
  - SPORT Loopback
    382
- Clock Signal Options
  383
- Frame Sync Options
  384
- Data Word Formats
  389
  - Word Length
    389
  - Data Packing and Unpacking
    390
  - Endian Format
    390
    
    Data Type
    391
    
    Companding
    392
- SPORT Control Registers and Data Buffers
  394
- Moving Data between SPORTS and Internal Memory
  415
  - DMA Block Transfers
    416
    
    Setting up DMA on SPORT Channels
    418
    
    SPORT DMA Parameter Registers
    419
    
    Single Word Transfers
    423
    
    SPORT DMA Chaining
    423
  - SPORT Programming Examples
    424
Serial Peripheral Interface Port

437
- Functional Description
  438
- SPI Interface Signals
  439
  - SPI Clock Signal (SPICLK)
    440
    
    SPI Slave Select Outputs (SPIDS0-3)
    441
    
    SPICLK Timing
    441
  - SPI Device Select Signal
    442
  - Master out Slave in (MOSI)
    442
  - Master in Slave out (MISO)
    442
- SPI General Operations
  443
  - SPI Enable
    444
  - Open Drain Mode (OPD)
    444
  - Master Mode Operation
    445
  - Slave Mode Operation
    446
  - Multimaster Conditions
    447
- SPI Data Transfer Operations
  448
  - Core Transmit and Receive Operations
    448
  - Spi Dma
    448
    
    Master Mode DMA Operation
    450
    
    Master Transfer Preparation
    452
  - Slave Mode DMA Operation
    453
    
    Slave Transfer Preparation
    454
  - Changing SPI Configuration
    456
  - Switching from Transmit to Receive DMA
    457
  - Switching from Receive to Transmit DMA
    458
  - DMA Error Interrupts
    460
  - DMA Chaining
    461
- SPI Transfer Formats
  462
  - Beginning and Ending an SPI Transfer
    464
- SPI Word Lengths
  465
  - 8-Bit Word Lengths
    466
  - 32-Bit Word Lengths
    467
  - Packing
    467
- SPI Interrupts
  468
- SPI Registers
  470
  - Control and Status Registers
    470
    
    Use of Dsxen Bits in SPIFLG for Multiple Slave SPI Systems
    472
    
    SPI Device Select Input Pin
    473
  - Buffering and Transmit/Receive Registers
    473
    
    SPI Transmit Data Buffer Register (TXSPI)
    474
    
    DMA Registers
    475
    
    SPI DMA Address Modifier Register (IMSPI)
    475
    
    SPI DMA Internal Index Register (IISPI)
    475
    
    SPI Receive Data Buffer Register (RXSPI)
    475
    
    SPI DMA Word Count Register (CSPI)
    476
  - Error Signals and Flags
    476
    
    Mode Fault Error (MME)
    476
    
    Transmission Error Bit (TUNF)
    477
    
    Reception Error Bit (ROVF)
    478
  - Programming Model
    478
    
    Master Mode Core Transfers
    479
    
    Slave Mode Core Transfers
    480
    
    Master Mode DMA Transfers
    481
    
    Slave Mode DMA Transfers
    483
    
    Chained DMA Transfers
    484
    
    Stopping Core Transfers
    485
    
    Stopping DMA Transfers
    486
    
    Switching from Transmit to Transmit/Receive DMA
    486
    
    Switching from Receive to Receive/Transmit DMA
    488
    
    DMA Error Interrupts
    489
11 Input Data Port

491
- Serial Inputs
  493
- Parallel Data Acquisition Port (PDAP)
  496
  - Masking
    498
  - Packing Unit
    498
    
    Packing Mode 11
    499
    
    Packing Mode 01
    500
    
    Packing Mode 00
    501
  - Clocking Edge Selection
    501
  - PDAP Strobe
    503
- FIFO Control and Status
  504
- FIFO to Memory Data Transfer
  505
  - Interrupt-Driven Transfers
    506
    
    Starting an Interrupt-Driven Transfer
    506
  - Interrupt-Driven Transfer Notes
    508
    
    DMA Transfer Notes
    510
  - DMA Channel Parameter Registers
    512
  - IDP (DAI) Interrupt Service Routines for Dmas
    513
- Input Data Port Programming Example
  514
12 Digital Audio Interface

523
- Structure of the DAI
  523
- DAI System Design
  524
- Signal Routing Unit
  525
  - Connecting Peripherals
    525
  - Pins Interface
    529
  - Pin Buffers as Signal Output Pins
    531
  - Pin Buffers as Signal Input Pins
    533
  - Bidirectional Pin Buffers
    534
- Making Connections in the SRU
  537
  - SRU Connection Groups
    539
    
    Group a Connections - Clock Signals
    540
    
    Group B Connections - Data Signals
    541
    
    Group C Connections - Frame Sync Signals
    542
    
    Group D Connections - Pin Signal Assignments
    543
    
    Group E Connections - Miscellaneous Signals
    545
    
    Group F - Pin Enable Signals
    547
- General-Purpose I/O (GPIO) and Flags
  548
- Miscellaneous Signals
  548
  - Relationship to the Core
    548
  - DAI Interrupts
    550
  - High and Low Priority Latches
    551
  - Rising and Falling Edge Masks
    552
- Using the SRU() Macro
  553
Precision Clock Generator

555
- Clock Outputs
  557
- Frame Sync Outputs
  558
  - Frame Sync
    558
  - Frame Sync Output Synchronization with External Clock
    559
- Phase Shift
  561
  - Phase Shift Settings
    562
  - Pulse Width
    563
    
    Bypass as a Pass through
    564
  - Bypass Mode
    564
    
    Bypass as a One Shot
    565
- PCG Programming Examples
  566
14 Peripheral Timer

571
- Timer Architecture
  571
- Timer Status and Control
  573
  - Timer Interrupts
    574
- Enabling a Timer
  575
- Timer Programming Examples
  584
15 System Design

591
- Pin Descriptions
  592
  - Pin Multiplexing
    592
  - Input Synchronization Delay
    594
  - Clock Derivation
    594
    
    Power Management Control Register
    595
  - RESET and CLKIN
    597
  - Reset Generators
    599
  - Interrupt and Peripheral Timer Pins
    602
  - Core-Based Flag Pins
    602
  - JTAG Interface Pins
    602
  - Phase-Locked Loop Startup
    603
- Conditioning Input Signals
  604
  - Input Pin Hysteresis
    604
- Designing for High Frequency Operation
  605
- Booting
  609
  - Parallel Port Booting
    611
- SPI Port Booting
  612
  - 32-Bit SPI Host Boot
    614
  - 16-Bit SPI Host Boot
    615
  - 8-Bit SPI Host Boot
    616
  - Slave Boot Mode
    618
  - Master Boot
    620
  - Booting from an SPI Flash
    622
  - Booting from an SPI Host Processor
    622
Registers Reference

625
- Control and Status System Registers
  625
- Processing Element Registers
  642
- Program Sequencer Registers
  645
  - Interrupt Mask Register (IMASK
    647
  - Interrupt Latch Register (IRPTL)
    647
  - Interrupt Mask Pointer Register (IMASKP)
    648
  - Interrupt Register (LIRPTL)
    652
  - Program Counter Register (PC
    655
  - Program Counter Stack Register (PCSTK
    656
  - Program Counter Stack Pointer Register (PCSTKP
    656
  - Status Stack Register (STS
    657
  - Fetch Address Register (FADDR
    657
  - Decode Address Register (DADDR
    657
  - Loop Address Stack Register (LADDR
    657
  - Current Loop Counter Register (CURLCNTR
    658
  - Loop Counter Register (LCNTR
    658
  - Timer Period Register (TPERIOD
    658
  - Timer Count Register (TCOUNT
    659
- Data Address Generator Registers
  659
  - Index Registers (IX
    659
  - Modify Registers (MX
    659
  - Length and Base Registers (Lx, Bx
    659
  - Alternate DAG Registers (IX', MX', Lx', Bx
    660
- Flag Value Register (FLAGS)
  661
- System Control Register (SYSCTL
  665
  - Emulation Registers
    668
    
    Hardware Breakpoint Control Register (BRKCTL
    668
    
    Emulation Control (EMUCTL) Register
    672
    
    Breakpoint (Psx, DMX, Iox) Registers
    676
    
    EEMUIN Register
    680
    
    Enhanced Emulation Status Register (EEMUSTAT
    680
    
    EEMUOUT Register
    683
    
    Emulation Clock Counter Registers
    683
- I/O Processor Registers
  684
  - Power Management Registers
    687
    
    Power Management Control Register (PMCTL
    688
  - Serial Port Registers
    691
    
    SPORT Serial Control Registers (Spctlx
    691
    
    SPORT Multichannel Control Registers (Spmctlxy
    701
    
    SPORT Receive Buffer Registers (Rxspx
    707
    
    SPORT Transmit Buffer Registers (Txspx
    707
    
    SPORT Divisor Registers (DIVX
    708
    
    SPORT Count Registers (Spcntx
    709
    
    SPORT Transmit Select Registers (Mtxcsy
    709
    
    SPORT Receive Select Registers
    710
    
    SPORT Transmit Compand Registers (Mtxccsy
    710
    
    SPORT Receive Compand Registers (Mrxccsy
    711
    
    SPORT DMA Index Registers (Iispx
    712
    
    SPORT DMA Modifier Registers (Imspx
    712
  - SPORT DMA Count Registers (Cspx)
    713
  - SPI Registers
    714
  - SPI Port Flags Register (SPIFLG)
    717
  - SPI Control Register (SPICTL)
    718
  - Shift Registers
    722
    
    SPI Receive Buffer Register (RXSPI)
    723
  - SPI Baud Rate Register (SPIBAUD)
    724
- SPI DMA Registers
  725
- Precision Clock Generator Registers
  764
  - Input Data Port Registers
    770
    
    Input Data Port DMA Control Registers
    774
    
    Control Register (IDP_PDAP_CTL)
    775
    
    Peripheral Timer Registers
    779
    
    Timer Configuration Registers (Tmxctl)
    780
    
    Timer Status Registers (Tmxstat)
    781
    
    DAI Registers
    783
    
    DAI Resistor Pull-Up Enable Register (DAI_PIN_PULLUP)
    785
    
    DAI Interrupt Controller Registers
    789
    
    Interrupt Controller
    791
Interrupt Vector

797

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