Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 636

Core Registers
Table A-4. ASTATx and ASTATy Register Bit Descriptions (Cont'd)
Bit Name
8 MU
9 MI
10 AF
11 SV
A-14
Description
Multiplier Floating-Point Underflow. Indicates if the last multiplier oper-
ation's result underflowed (if set, = 1) or did not underflow
(if cleared, = 0). The multiplier updates MU for all fixed- and float-
ing-point multiplier operations. For floating-point results, the processor
sets MU and the MUS bit in the STKYx/y register if the floating-point
result underflows (unbiased exponent < –126). Denormal operands are
treated as zeros, therefore they never cause underflows. For fixed-point
results, the processor sets MU and the MUS bit in the STKYx/y register if
the result of the multiplier operation is:
• Twos-complement, fractional: with upper 48 bits all zeros or all ones,
lower 32 bits not all zeros
• Unsigned, fractional: with upper 48 bits all zeros, lower 32 bits not all
zeros
If the multiplier operation directs a fixed-point, fractional result to an MR
register, the processor places the underflowed portion of the result in
MR0.
Multiplier Floating-Point Invalid Operation. Indicates if the last multi-
plier operation's input was invalid (if set, = 1) or valid (if cleared, = 0).
The multiplier updates MI for floating-point multiplier operations. The
processor sets MI and the MIS bit in the STKYx/y register if the ALU
operation:
• Receives a NAN input operand
• Receives an Infinity and zero as input operands
ALU Floating-Point Operation. Indicates if the last ALU operation was
floating-point (if set, = 1) or fixed-point (if cleared, = 0). The ALU
updates AF for all fixed-point and floating-point ALU operations.
Shifter Overflow. Indicates if the last shifter operation's result overflowed
(if set, = 1) or did not overflow (if cleared, = 0). The shifter updates SV for
all shifter operations. The processor sets SV if the shifter operation:
• Shifts the significant bits to the left of the 32-bit fixed-point field
• Tests, sets, or clears a bit outside of the 32-bit fixed-point field
• Extracts a field that is past or crosses the left edge of the 32-bit
fixed-point field
• Performs a LEFTZ or LEFTO operation that returns a result of 32
ADSP-2126x SHARC Processor Hardware Reference