Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 792

I/O Processor Registers
An explicit read resets these register values to zero, except for the
(IDP FIFO samples exceeded interrupt) bit. The interrupt on
FO_GTN_INT
the
IDP_FIFO_GTN_INT
caused the interrupt goes away.
DAI_IRPTL_L (0x2489)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRU_EXTMISCA3_INT
SRU_EXTMISCA2_INT
SRU_EXTMISCA1_INT
SRU_EXTMISCA0_INT
SRU_EXTMISCB5_INT
SRU_EXTMISCB4_INT
SRU_EXTMISCB3_INT
IDP_DMA5_INT
IDP_DMA4_INT
IDP_DMA3_INT
IDP_DMA2_INT
IDP_DMA1_INT
Figure A-74. DAI_IRPTL_L Register
A read resets the value to zero, except under the following condition—the
IDP_FIFO_GTN_INT
read. This bit is cleared when the cause of this interrupt is zero.
A-170
bit clears automatically when the condition that
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
bit is not cleared when
ADSP-2126x SHARC Processor Hardware Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
DAI_IRPTL_H/L
IDP_FI-
IDP_DMA6_INT
IDP_DMA7_INT
Reserved
ISRU_EXTMISCB0_INT
ISRU_EXTMISCB1_INT
ISRU_EXTMISCB2_INT
Reserved
IDP_FIFO_GTN_INT
IDP FIFO Samples
Exceeded Interrupt
IDP_FIFO_OVR_INT
IDP FIFO Overflow
Interrupt
IDP_DMA0_INT
registers are