Data Addressing Stalls; Addressing Circular Buffers - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

DAG Operations
The following example instruction accepts up to 6-bit modifiers:
F6 = F1 + F2,PM(I8,0x0B) = ASTAT; /* PM address = I8,

Note that pre-modify addressing operations must not change the
memory space of the address.

Data Addressing Stalls

As explained in the previous sections, the instruction sequence stalls for
one cycle if a read-after-write hazard is detected on a DAG register. For
example, the following sequence automatically generates a one cycle stall.
I0 = R0;
DM(I0,M0) = R1;
DAG conditional addressing can generate stalls if a post-modify instruc-
tion is aborted.
R2 = R3 – R4;
IF EQ DM(I1,M1) = R1;
DM(I1,M2) = R2;
Note that even if the second instruction finds its condition true, a stall is
still inserted. Furthermore, if the second instruction is annulled because
the condition was false, then a stall is inserted in the address computation
(decode) stage of the third instruction. Note that a stall is generated only
if the above sequence is executed back-to-back.

Addressing Circular Buffers

The DAGs support addressing circular buffers. This is defined as address-
ing a range of addresses which contain data that the DAG steps through
repeatedly, "wrapping around" to repeat stepping through the range of
addresses in a circular pattern. To address a circular buffer, the DAG steps
the index pointer (
4-12
/* Compute setting flags */
/* Flag is used immediately */
/* Updated I1 is used immediately */
register) through the buffer, post-modifying and
I
ADSP-2126x SHARC Processor Hardware Reference
I8 = I8 + 0x0B */