Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 673

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Table A-17. Emulation Control Register (EMUCTL) Definitions

ADSP-2126x SHARC Processor Hardware Reference

Emulator Function Enable. Enables processor emulation func-

tions. (0 = ignore breakpoints and emulator interrupts, 1=respond

to breakpoints and emulator interrupts)

Emulator Interrupt Enable. Enables the emulation logic to recog-

nize external emulator interrupts. (0 = disable, 1 = enable)

Enable Autostop on Breakpoint. Enables the

ADSP-2126x DSP to generate an external emulator interrupt

when any breakpoint event occurs. (0=disable, 1=enable)

Enable Single Step Mode. Enables single-step operation.

(0=disable, 1=enable)

Software Reset of the ADSP-2126x. Resets the ADSP-2126x DSP

in the same manner as the external

must be cleared by the emulator.(0=normal operation, 1=reset)

Enable the BRKOUT pin. Enables the

pin at high impedance state, 1 =

Stop IOP DMAs in EMU Space. Disables all DMA requests when

the DSP is in emulation space. Data that is currently in the SPI or

SPORT DMA buffers is held there unless the internal DMA

request was already granted. IOSTOP causes incoming data to be

held off and outgoing data to cease. Because SPORT receive data

cannot be held off, it is lost and the overrun bit is set.

(0 = I/O continues, 1 = I/O Stops)

Negate program memory data address breakpoint. Enable break-

point events if the address is greater than the end register value OR

less than the start register value. This function is useful to detect

index range violations in user code.

(0 = disable breakpoint, 1 = enable breakpoint)

Instruction address and program memory breakpoint negates have

an effect latency of four (4) core clock cycles.

Registers Reference

pin. The SYSRST bit

pin operation.

pin enabled)