Program Sequencer
INSTRUCTION
CACHE
FLAGS
CONDITION
LOOP CONTROL
LOGIC
CORE
TIMER
OTHER
INTERRUPTS
INSTRUCTION PIPELINE
INTERRUPT
PROGRAM
CONTROLLER
COUNTER STACK
48
NEXT ADDRESS MULTIPLEXER
24
PM ADDRESS BUS
PM DATA BUS
Figure 3-1. Program Sequencer Block Diagram
ADSP-2126x SHARC Processor Hardware Reference
3-3
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