Register Writes And Effect Latency; Serial Port Control Registers (Spctlx) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPORT Control Registers and Data Buffers
Table 9-5. SPORT Registers (Cont'd)
IOP Register
Address
0xC14 MR1CCS3
0xC60 TXSP0A
0xC61 RXSP0A
0xC62 TXSP0B
0xC63 RXSP0B
0xC64 TXSP1A
0xC65 RXSP1A
0xC66 TXSP1B
0xC67 RXSP1B

Register Writes and Effect Latency

SPORT register writes are internally completed at the end of three (worst
case) or two (best case) core clock cycles. The newly written value to the
SPORT register can be read back on the next cycle. Reads of the SPORT
registers take four core clock cycles.
After a write to a SPORT register, control and mode bit changes take
effect in the second serial clock cycle. The serial ports are ready to start
transmitting or receiving three serial clock cycles after they are enabled in
the control register. No serial clocks are lost from this point on.
SPCTLx

Serial Port Control Registers (SPCTLx)

The main control register for each serial port is the Serial Port Control
register,
SPCTLx
Registers (SPCTLx)" on page
9-50
Reset Description
0x0000 0000 SPORT1 Multichannel Receive Compand select 3
(Channels 127–96)
0x0000 0000 SPORT0 Transmit Data Buffer; A channel data
0x0000 0000 SPORT0 Receive Data Buffer; A channel data
0x0000 0000 SPORT0 Transmit Data Buffer; B channel data
0x0000 0000 SPORT0 Receive Data Buffer; B channel data
0x0000 0000 SPORT1 Transmit Data Buffer; A channel data
0x0000 0000 SPORT1 Receive Data Buffer; A channel data
0x0000 0000 SPORT1 Transmit Data Buffer; B channel data
0x0000 0000 SPORT1 Receive Data Buffer; B channel data
. These registers are described in
A-69. When changing operating modes,
ADSP-2126x SHARC Processor Hardware Reference
"SPORT Serial Control