Reading From An External Device Or Memory - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Parallel Port Operation
In a read cycle, the
upper 16 bits of the external address have changed, this cycle is always pre-
ceded by an
ALE
, are driven on the
0
on the rising edge of
read cycle, the external address is provided entirely by the external latch,
and data is sampled from the
cycles can be lengthened by configuring the parallel port data cycle dura-
tion bits in the
In a write cycle,
bits of the external address have changed, this cycle is always preceded by
an cycle. In 8-bit mode, the lower 8 bits of the address are driven on
ALE
the pins and data is driven on the
AD15–8
address bits are not driven in the write cycle, the external address is pro-
vided entirely by the external latch, 16-bit data is driven onto the
pins, and data is written to the external device on the rising edge of the
signal. Address and data are driven before the falling edge of
serted after the rising edge to ensure enough setup and hold time with
respect to the
WR
parallel port data cycle duration bits in the

Reading From an External Device or Memory

The parallel port has a two stage data FIFO for receiving data (
the first stage, a 32-bit register (
data pins and packs the 8- or 16-bit data into 32 bits. Once the 32-bit
data is received in
ister ( ). Once the receive FIFO is full, the chip cannot initiate any
RXPP
more external data transfers. The
core or I/O processor (for DMA).

The
PPTRAN
8-6
and signals are inactive and
WR ALE
cycle. In 8-bit mode, the lower 8 bits of the address,
pins, and data is sampled from the
AD15–8
. In 16-bit mode, address bits are not driven in the
RD
AD15–0
register.
PPCTL
and are inactive and
RD ALE
signal. Write cycles can be lengthened by configuring the
PPSI
, the data is transferred into the second 32-bit reg-
PPSI
bit must be zero in order to be read.
ADSP-2126x SHARC Processor Hardware Reference
pins at the rising edge of
is strobed. If the upper 16
WR
pins. In 16-bit mode,
AD7–0
register.
PPCTL
) provides an interface to the external
register acts as the interface to the
RXPP
is strobed. If the
RD
EA7–
pins
AD7–0
. Read
RD
AD15-0
WR
and deas-
WR
). In
RXPP