Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 12

Contents
Boundary Register ................................................................... 6-8
Built-In Self-Test Operation (BIST) ........................................ 6-9
EMUIDLE Instruction ........................................................... 6-9
Private Instructions ....................................................................... 6-9
References .................................................................................... 6-9
I/O PROCESSOR
General Procedure for Configuring DMA ...................................... 7-2
IOP/Core Interaction Options ...................................................... 7-3
Interrupt-Driven I/O .............................................................. 7-3
Polling/Status Driven I/O ....................................................... 7-7
DMA Controller Operation .................................................... 7-8
Chaining DMA Processes .................................................. 7-10
Transfer Control Block Chain Loading (TCB) ................... 7-13
Setting Up and Starting the Chain .................................... 7-14
Setting Up and Starting Chained DMA over the SPI ......... 7-14
Inserting a TCB in an Active Chain .................................. 7-16
Setting Up DMA Channel Allocation and Priorities ............... 7-17
Managing DMA Channel Priority ..................................... 7-18
DMA Bus Arbitration ....................................................... 7-19
Setting Up DMA Parameter Registers .......................................... 7-21
DMA Transfer Direction ....................................................... 7-21
Data Buffer Registers ............................................................ 7-23
Port, Buffer, and DMA Control Registers .............................. 7-24
Addressing ............................................................................ 7-26
xii ADSP-2126x SHARC Processor Hardware Reference