Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 576

Enabling a Timer
register. To enable all three timers in parallel, set all the
TMSTAT
bits in the
TMSTAT
Before enabling a timer, always program the corresponding timer's Con-
figuration (
TMxCTL
mode, the polarity of the
ior. Do not alter the operating mode while the timer is running. For more
information on the
(TMxCTL)" on page
The timer enable and disable timing appears in
TIMER ENA BLE
TIMEN
CCLK
PWMOUT
TIMER D ISABLE
CCLK
Figure 14-2. Timer PWM Enable and Disable Timing
When the timer is enabled, the Count register is loaded according to the
operation mode specified in the
abled, the Counter registers retain their state; when the timer is
re-enabled, the counter is reinitialized based on the operating mode. The
software should never write the counter value directly.
14-6
register.
) register. This register defines the timer's operating
TIMERx
register, see
TMxCTL
A-157.
SET TIMER
ENABLED
TCOUNT TCOUNT
= XX = XX
SET TIMER
TIMDIS DISABLED
TCOUNT TC OUNT
= M = M + 1
TMxCTL
ADSP-2126x SHARC Processor Hardware Reference
signal, and the timer's interrupt behav-
"Timer Configuration Registers
Figure
TCOUNT TCOUNT TCOUNT
= 1 = 2
TCOUNT TCOUNT
= M + 1 = M + 1
register. When the timer is dis-
TIMxEN
14-2.
TCOUNT
= 3 = 4
T MxPRD = 0x2
T MxW = 0x1