Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 767

Table A-42. PCG_CTLB_0 Register Bit Descriptions
Bits Name
19–0 FSBDIV
29–20 FSBPHASE_HI
30 ENFSB
31 ENCLKB
PCG_CTLB_1 (0x24C3)
CLKBSOURCE
Clock B Source
FSBSOURCE
Frame Sync B Source
Figure A-59. PCG_CTLB_1 Register
ADSP-2126x SHARC Processor Hardware Reference
Description
Divisor for Frame Sync B.
Phase for Frame Sync B. This field represents the upper half
of the 20-bit value for the channel B frame sync phase. The
phase represents the number of input clocks remaining in the
first frame after the signal is enabled.
See also FSBPHASE_LO (Bits 29-20) in PCG_CTLB_1
shown in
Enable Frame Sync B.
0 = Frame Sync B generation disabled
1 = Frame Sync B generation enabled
Enable Clock B.
0 = Clock B generation disabled
1 = Clock B generation enabled
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
Registers Reference
Figure A-59 on page A-145.
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
FSBPHASE_LO
Frame Sync B
Phase 9:0
CLKBDIV
CLK B Divisor
A-145