When
= 1 and
DIFS
sync is output at its programmed interval regardless of whether new data is
available in the transmit buffer. The processor generates the transmit
signal at the frequency specified by the value loaded in the
SPORTx_FS
register. If a frame sync occurs when the transmitter FIFO is empty, the
MSB or LSB (depending on how the
ous word is transmitted. When
signal is generated regardless of the receive data buffer status.
SPORTx_FS
Depending on the SPORT operating mode, the Transmitter Underflow
(
or
TUVF_A
TUVF_B
when a frame sync occurs; or a Receive Overflow bit (
set if the receive buffers are full and a new data word is received.
If the internally-generated frame sync is used and
the transmit data register is required to start the transfer.
Data Word Formats
The format of the data words transmitted over the serial ports is config-
ured by the
DTYPE
registers.
Word Length
Serial ports can process word lengths of 3 to 32 bits for Serial and Multi-
channel modes and 8 to 32 bits for I
using the 5-bit
Table 9-1 on page 9-10
The value of
SLEN
= serial word length – 1
SLEN
ADSP-2126x SHARC Processor Hardware Reference
= 1, the internally-generated transmit frame
SPTRAN
DIFS
) bit is set if the transmit buffer does not have new data
,
,
, and
LSBF
SLEN
field in the
SLEN
SPCTLx
for further information.
is:
bit in
LSBF
SPCTL
= 1 and
= 0, a receive
SPTRAN
ROVF_A
DIFS
bits of the
PACK
SPCTLx
2
S mode. Word length is configured
Control registers. Refer to
Serial Ports
DIV
is set) of the previ-
or
) is
ROVF_B
=0, a single write to
control
9-39
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