Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 114

The sequencer uses the blocks shown in
tions. The sequencer's address multiplexer selects the value of the next
fetch address from several possible sources. The fetched address enters the
instruction pipeline, made up of the fetch address register, decode address
register, and program counter (
24-bit addresses of the instructions currently being fetched, decoded, and
executed. The
return addresses and top-of-loop addresses. All addresses generated by the
sequencer are 24-bit program memory instruction addresses.
The sequencer handles a series of operations, described in these sections:
• "Instruction Pipeline" on page 3-4
• "Instruction Cache" on page 3-5
• "Branches and Sequencing" on page 3-11
• "Loop and Status Stacks and Sequencing" on page 3-16
• "Conditional Sequencing" on page 3-17
• "Loops and Sequencing" on page 3-25
• "SIMD Mode and Sequencing" on page 3-36
• "Timer and Sequencing" on page 3-46
• "Interrupts and Sequencing" on page 3-48
Refer to Figure 3-1
are related.
3-2
PC
register, in conjunction with the PC stack register, stores
PC
for a description of how each of the functional blocks
ADSP-2126x SHARC Processor Hardware Reference
Figure 3-1
) register. These registers contain the
to execute instruc-