Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 736

I/O Processor Registers
Each of these modules is separated from each other by the SRU, and their
input and output signals (the "junctions") may only be connected via the
SRU.
Clock Routing Control Registers
(SRU_CLKx, Group A)
The Clock Routing Control registers route a serial data clock, a sample
clock, and signals to the SPORTs and the Input Data Port (IDP) chan-
nels. Each of the clock inputs specified are connected to a clock source,
based on the five bit values in the
sion clock generators is in external source mode, the
and/or
SRU_CLK3[9:5]
The Clock Routing Control registers correspond to the Group A clock
sources, listed in
connected using these read/write registers:
•
SRU_CLK0
•
SRU_CLK1
•
SRU_CLK2
•
SRU_CLK3
A-114
Table
bits specify the source.
Table A-34. Thirty-two possible clock sources can be
, described in Figure A-34
, described in Figure A-35
, described in Figure A-36 on page A-116
, described in Figure A-37 on page A-116
ADSP-2126x SHARC Processor Hardware Reference
A-34. When either of the preci-
SRU_CLK3[4:0]