Broadcast Register Loads - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

ADSP-2126x Memory Map
For information on complementary (implicit) registers in SIMD mode
accesses, see "Secondary Processor Element (PEy)" on page
more information on complementary (implicit) memory locations in
SIMD mode accesses, see

Broadcast Register Loads

The DSP's
BDCST1
register loading. When broadcast loading is enabled, the DSP writes to
complementary registers or complementary register pairs in each process-
ing element on writes that are indexed with DAG1 register
=1) or DAG2 register
BDCST1
similar to SIMD mode accesses in that the DSP transfers both an explicit
(named) location and an implicit (unnamed, complementary) location.
However, broadcast loading only influences writes to registers and writes
identical data to these registers. Broadcast mode is independent of SIMD
mode.
Table 5-2 shows examples of explicit and implicit effects of broadcast reg-
ister loads to both processing elements. Note that broadcast loading only
effects loads of data registers (register file); broadcast loading does not
effect register stores or loads to other system registers. Furthermore,
broadcast loads only work on register loads; broadcast loading cannot be
used for memory writes. For more information on broadcast loading, see
"Accessing Memory" on page
Table 5-2. Register Load Dual PE Broadcast Operation
Instruction
(Explicit, PEx Operation)
Rx = dm(i1,ma);
Rx = pm(i9,mb);
Rx = dm(i1,ma), Ry = pm(i9,mb);
1 The post increment in the explicit operation is performed before the implicit instructions are
executed.
5-20
"Accessing Memory" on page
and bits in the
BDCST9
(if
I9 BDCST9
5-22.
1
ADSP-2126x SHARC Processor Hardware Reference
register control broadcast
MODE1
=1). Broadcast load accesses are
(Implicit, PEy operation)
Sx = dm(i1,ma);
Sx = pm(i9,mb);
Sx = dm(i1,ma), Sy = pm(i9,mb);
5-19. For
5-22.
(if
I1