Setting Computational Modes; 32-Bit Floating-Point Format (Normal Word) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Setting Computational Modes

Setting Computational Modes
The register controls the operating mode of the processing ele-
MODE1
ments. Table A-2 on page A-5
in control computational modes:
MODE1
• Floating-point data format. Bit 16 (
tional units to round floating-point data to 32 bits (if 1) or round
to 40 bits (if 0).
• Rounding mode. Bit 15 (
round results with round-to-zero (if 1) or round-to-nearest (if 0).
• ALU saturation. Bit 13 (
saturate results on positive or negative fixed-point overflows (if 1)
or return unsaturated results (if 0).
• Short word sign extension. Bit 14 (
units to sign extended short word 16-bit data (if 1) or zero-fill the
upper 16 bits (if 0).
• Secondary processor element (PEy). Bit 21 (
tations in PEy (SIMD mode) (if 1) or disables PEy Single
Instruction Single Data (SISD mode) (if 0).

32-Bit Floating-Point Format (Normal Word)

In the default mode of the DSP (
support a single-precision floating-point format, which is specified in the
IEEE 754/854 standard. For more information on this standard, see
"Numeric Formats" on page
ble for single-precision floating-point operations in all respects except:
2-12
lists all the bits in
) directs the computational units to
TRUNC
) directs the computational units to
ALUSAT
RND32
2-3. This format is IEEE 754/854 compati-
ADSP-2126x SHARC Processor Hardware Reference
. The following bits
MODE1
) directs the computa-
RND32
) directs the computational
SSE
) enables compu-
PEYEN
bit=1), the multiplier and ALU