Spi Port Flags Register (Spiflg) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

SPI Port Flags Register (SPIFLG)

This register's address is 0x1001. The reset value for this register is
0x0F80.The
SPIFLG
lines when the SPI is enabled as a master.
SPIFLG (0x1001)
Reserved
SPIDSx
SPI Device Select Control
1=Disable
0=Enable
ISSS
Status of Input Slave Select Pin
Figure A-29. SPIFLG Register
Table A-26. SPIFLG Register Bits
Bit Name
3–0 DSxEN
(3–0)
6–4 Reserved
7 ISSS
11–8 SPIFLGx
(3–0)
31–12 Reserved
ADSP-2126x SHARC Processor Hardware Reference
register is used to enable individual SPI slave select
31 30 29 28 27 26 24 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10
9
0 0 0 0 1 1 1
Function
SPI Device Select Bits. This bit enables or disables if set, (= 1 or if
cleared = 0) the corresponding flag output to be used for an SPI
slave-select.
Input Service Select Bit. This read-only bit reflects the status of
the slave select input pin.
SPI Device Select Control. This bit if cleared, (= 0) selects a corre-
sponding flag output to be used for SPI slave-select.
Registers Reference
0 0 0 0 0 0 0
8 7 6 5 4 3 2 1
1 0 0 0 0 0 0 0
0
Reserved
0
0
DSxEN
SPI Device Select Enable
1=Enable
0=Disable
Reserved
A-95