Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 705

For a detailed description of the bits in the
Table A-24.
Table A-24. SPMCTLxy Register Bit Descriptions
Bits Name
0 MCEA
4–1 MFD
11–5 NCH
ADSP-2126x SHARC Processor Hardware Reference
Definition
Multichannel Mode Enable. Standard and Multichannel modes
only. One of two configuration bits that enable and disable mul-
tichannel mode on serial port channels. See also, OPMODE on
page A-26.
0 = Disable multichannel operation
1 = Enable multichannel operation if OPMODE = 0
Multichannel Frame Delay. Set the interval, in number of serial
clock cycles, between the multichannel frame sync pulse and the
first data bit. These bits provide support for different types of T1
interface devices. Valid values range from 0 to 15 with bits
SPMCTL01 [4:1] or SPMCTL23[4:1] or SPMCTL45[4:1]. Val-
ues of 1 to15 correspond to the number of intervening serial
clock cycles. A value of 0 corresponds to no delay. The multi-
channel frame sync pulse is concurrent with first data bit.
Number of Multichannel Slots (minus one). Select the number
of channel slots (maximum of 128) to use for multichannel oper-
ation. Valid values for actual number of channel slots range from
1 to 128. Use this formula to calculate the value for NCH: NCH
= Actual number of channel slots – 1.
Registers Reference
register, refer to
SPMCTLxy
A-83