Sport Dma Index Registers (Iispx; Sport Dma Modifier Registers (Imspx - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

I/O Processor Registers

SPORT DMA Index Registers (IISPx)

The addresses of the
IISP0A – 0xC40
IISP1A – 0xC48
IISP2A – 0x440
IISP3A – 0x448
IISP4A – 0x840
IISP5A – 0x848
The reset value for these registers is undefined. The
bits wide and it holds an address and acts as a pointer to memory for a
DMA transfer.
I/O Processor.

SPORT DMA Modifier Registers (IMSPx)

The addresses of the
IMSP0A – 0xC41
IMSP1A – 0xC49
IMSP2A – 0x441
IMSP3A – 0x449
IMSP4A – 0x841
IMSP5A – 0x849
The reset value for these registers is undefined. The
bits wide and it provides the increment or step size by which an
ister is post-modified during a DMA operation.
"I/O Processor" in Chapter 7, I/O Processor.
A-90
registers are:
IISPx
IISP0B – 0xC44
IISP1B – 0xC4C
IISP2B – 0x444
IISP3B – 0x44C
IISP4B – 0x844
IISP5B – 0x84C
For more information, see "I/O Processor" in Chapter 7,
registers are:
IMSPx
IMSP0B – 0xC45
IMSP1B – 0xC4D
IMSP2B – 0x445
IMSP3B – 0x44D
IMSP4B – 0x845
IMSP5B – 0x84D
ADSP-2126x SHARC Processor Hardware Reference
register is 19
IISPx
register is 16
IMSPx
IISPx
For more information, see
reg-