Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 805

Flag update. The DSP's update to status flags occurs at the end of the
cycle in which the status is generated and is available on the next cycle.
Harvard architecture. DSPs use memory architectures that have separate
buses for program and data storage. The two buses let the DSP get a data
word and an instruction simultaneously.
Hold time cycle. This is an inactive bus cycle that the DSP automatically
generates at the end of a read or write (depending on the parallel port
access mode) to allow a longer hold time for address and data. The
address—and data, if a write—remains unchanged and is driven for one
cycle after the read or write strobes are deasserted.
I/O processor register. One of the control, status, or data buffer registers
of the DSP's on-chip I/O processor.
Idle cycle. This is an inactive bus cycle that the DSP automatically gener-
ates (depending on the parallel port access mode) to avoid data bus driver
conflicts. Such a conflict can occur when a device with a long output dis-
able time continues to drive after RD is deasserted while another device
begins driving on the following cycle.
IDLE. An instruction that causes the processor to cease operations, hold-
ing its current state until an interrupt occurs. Then, the processor services
the interrupt and continues normal execution.
Index registers. An index register is a Data Address Generator (DAG) reg-
ister that holds an address and acts as a pointer to memory.
Indirect branches. These are JUMP or CALL/return instructions that use
a dynamic—changes at runtime—address that comes from the PM data
address generator.
Inexact flags. An inexact flag is an exception flag whose bit position is
inexact.
ADSP-2126x SHARC Processor Core Manual G-5