Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 704

I/O Processor Registers
SPMCTL45
(0x804)
DMACHS5B
SPORT3 Channel B Status
DMA Chaining Status
DMACHS5A
SPORT3 Channel A Status
DMA Chaining Status
DMACHS4B
SPORT2 Channel B Status
DMA Chaining Status
DMACHS4A
SPORT2 Channel A Status
DMA Chaining Status
DMAS5B
SPORT3 Channel B Status
DMA Status
DMAS5A
SPORT3 Channel A Status
DMA Status
Reserved
SPL
SPORT Loopback
SPORT3 A to C, B to D Only
NCH
Number of Channels – 1
Figure A-26. SPMCTL45 Registers – Multichannel Mode
A-82
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
15 14 13 12 11 10
9
0 0 0 0 0 0 0
ADSP-2126x SHARC Processor Hardware Reference
0 0 0 0 0 0 0
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 0
0
CHNL
Current Channel Status
(read-only)
MCEB
Multichannel Enable
B Channels
1=Enable
0=Disable
DMAS4A
SPORT2 Channel
A Status
DMA Status
DMAS4B
SPORT2 Channel
B Status
DMA Status
0
0
MCEA
Multichannel Enable
A Channels
1=Enable
0=Disable
MFDx
Multichannel Frame Delay