Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 283

The ADSP-2126x emulation features halt the processor at a predefined
point to examine the state of the processor, execute arbitrary code, restore
the original state, and continue execution.

The ADSP-2126x emulation features are a superset of the
ADSP-21160 DSP emulation features. All emulation features sup-
ported by previous SHARC DSPs are supported on the
ADSP-2126x. The set of features on which JTAG ICE designs rely
are supported in an identical fashion on ADSP-2126x. The DSP
can be used with the ADSP-2106x SHARC JTAG ICE hardware.
There are several changes/extensions to the base functionality of the
ADSP-2116x DSP emulation capability, which require changes in the
JTAG ICE software for ADSP-2126x support. These extensions include:
• New registers for added functionality:
EEMUOUT
• A new JTAG instruction to support these additional registers:
EEMUINDATA
• New functionality to allow the tools software to support statistical
profiling.
• In addition to the IEEE boundary scan functionality, the DSP
offers support for background telemetry, user-definable breakpoint
interrupts, and cycle counting.
Several on-chip facilities are directly accessed through the JTAG interface.
These facilities are listed in
ities are only indirectly accessible. To indirectly access the facilities that do
not appear in Table
to/from the
PX
the core execute the instruction, and then scan the
instruction is a
ADSP-2126x SHARC Processor Hardware Reference
, and
SHADOW_SHIFT
, , and
EEMUOUTDATA
Table 6-2 on page
6-2, scan the instruction which moves data of interest
register, scan the
PX
write).
PX
JTAG Test Emulation Port
EEMUCTL
.
.
EEMUCTL
6-6. Other emulation facil-
data (if the instruction is a
PX
, ,
EEMUSTAT EEMUIN
read), let
PX
register out (if the
6-3
,