Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 434

SPORT Programming Examples
dm(SPCTL5) = r0;
dm(SPMCTL45) = r0;
SPORT_DMA_setup:
/* SPORT 5 Internal DMA memory address */
r0 = tx_buf5a;
/* SPORT 5 Internal DMA memory access modifier
r0 = 1;
/* SPORT 5 Number of DMA transfers to be done */
r0 = @tx_buf5a;
/* SPORT 4 Internal DMA memory address */
r0 = rx_buf4a;
/* SPORT 4 Internal DMA memory access modifier */
r0 = 1;
/* SPORT 4 Number of DMA5 transfers to be done */
r0 = @rx_buf4a;
/* set internal loopback bit for SPORT4 & SPORT5 */
bit set ustat3 SPL;
dm(SPMCTL45) = ustat3;
/* Configure SPORT5 as a transmitter */
/* internally generating clock and frame sync */
/* CLKDIV = [fCCLK(200 MHz)/4 x FSCLK(20 MHz)] – 1 = 0x004 */
/* FSDIV = [FSCLK(20 MHz)/TFS(.625 MHz)] – 1 = 31 = 0x001F */
R0 = 0x001F0004;
ustat4 = SPEN_A|
SLEN32|
FSR|
SPTRAN|
SDEN_A|
IFS|
ICLK;
9-84
dm(IISP5A) = r0;
dm(IMSP5A) = r0;
dm(CSP5A) = r0;
dm(IISP4A) = r0;
dm(IMSP4A) = r0;
dm(CSP4A) = r0;
dm(DIV5) = R0;
/* Enable Channel A */
/* 32-bit word length */
/* Frame Sync Required */
/* Transmit on enabled channels */
/* Enable Channel A DMA */
/* Internally Generated Frame Sync */
/* Internally Generated Clock */
ADSP-2126x SHARC Processor Hardware Reference
*/