Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 771

Input Data Port Control Register
(IDP_CTL)
The
IDP_CTL[31:8]
eight channels.
IDP_CTL (0x24B0)
IDP_SMODE7
Serial Mode Input Select 7
IDP_SMODE6
Serial Mode Input Select 6
15 14 13 12 11 10
IDP_SMODE2
Serial Mode Input Select 2
IDP_SMODE1
Serial Mode Input Select 1
IDP_SMODE0
Serial Mode Input Select 0
IDP_ENABLE
Input data port Enable
Figure A-62. IDP_CTL Register
Table A-46. IDP_CTL Register
Bits Name
3–0 IDP_NSET
4 IDP_BHD
ADSP-2126x SHARC Processor Hardware Reference
bits control the input format modes for each of the
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
9 8
0 0 0 0 0 0 0 0
Description
Monitored number of FIFO entries where N > samples
raises Interrupt Controller bit 8.
IDP Buffer Hang Disable. Reads of an empty FIFO or
writes to a full FIFO make the core hang. This condition
continues until the FIFO has valid data (in the case of
reads) or the FIFO has at least one empty location (in the
case of writes).
1 = Core hang is disabled
0 = Core hang is enabled
Registers Reference
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
IDP_SMODE3
Serial Mode Input Select 3
IDP_SMODE4
Serial Mode Input Select 4
IDP_SMODE5
Serial Mode Input Select 5
IDP_NSET
Monitor FIFO Entries
IDP_BHD
Buffer Hang Disable
IDP_DMA_EN
IDP DMA Enable
IDP_CLROVER
Clear FIFO Overflow
A-149