Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 651

Table A-9. IRPTL, IMASK, IMASKP Register Bit Descriptions (Cont'd)
Bit Name
11 P0I
12 P1I
13 P2I
14 P3I
15 P4I
16 P5I
17 P14I
18 P15I
19 P16I
20 CB7I
21 CB15I
22 TMZLI
23 FIXI
24 FLTOI
25 FLTUI
26 FLTII
27 EMULI
ADSP-2126x SHARC Processor Hardware Reference
Definition
Programmable Interrupt 0. A P0I interrupt occurs when the
default/programmed peripheral sets (= 1) this bit.
Programmable Interrupt 1. See P0I
Programmable Interrupt 2. See P0I
Programmable Interrupt 3. See P0I
Programmable Interrupt 4. See P0I
Programmable Interrupt 5. See P0I
Programmable Interrupt 14. See P0I
Programmable Interrupt 15. See P0I
Programmable Interrupt 16. See P0I
DAG1 Circular Buffer 7 Overflow Interrupt. A circular buffer over-
flow occurs when the DAG circular buffering operation increments the
I7 register past the end of the buffer.
DAG2 Circular Buffer 15 Overflow Interrupt. A circular buffer over-
flow occurs when the DAG circular buffering operation increments the
I15 register past the end of the buffer.
Core Timer Expired (Low Priority) Interrupt. A TMZLI occurs when
the timer decrements to zero. (Refer to TMZHI)
Fixed-Point Overflow Interrupt. Refer to the status registers for the
execution units (ASTATx/y, STKYx/y).
Floating-Point Overflow Interrupt. Refer to the status registers for the
execution units (ASTATx/y, STKYx/y).
Floating-Point Underflow Interrupt. Refer to the status registers for
the execution units (ASTATx/y, STKYx/y).
Floating-Point Invalid Operation Interrupt. Refer to the status regis-
ters for the execution units (ASTATx/y, STKYx/y).
Emulator Low Priority Interrupt. An EMULI occurs during Back-
ground telemetry channels (BTC). This interrupt has a lower priority
than EMUI, but higher priority than software interrupts.
Registers Reference
A-29