Parallel Data Acquisition Port (Pdap) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Parallel Data Acquisition Port (PDAP)

SERIAL CLOCK
IDPx_CLK_I
FRAME SYNC (L/R)
IDPx_FS_I
LEFT-JUSTIFIED
SAMPLE PAI R
LSB n-1
SERIAL DATA
IDPx_DAT_I
FRAME [n-1]
RIGHT
Figure 11-4. Timing in Left-justified Sample Pair Mode
S ERIAL CLOCK
IDPx_CLK_I
FRAME SYNC (L/R)
IDP x_FS _I
I 2 S S ERIAL DATA
IDPx_DAT_I
F RAME [n-1 ]
Figure 11-5. Timing in I
Parallel Data Acquisition Port (PDAP)
The input to channel 0 of the IDP is multiplexed, and may be used either
in the serial mode, described in
Parallel Input mode. Serial or parallel input is selected by setting
bit 31 in the
DAP_EN
the clock input for channel 0 is used to latch parallel sub words. Multiple
latched parallel sub-word samples may be packed into 32-bit words for
11-6
MSB n
0 63 62
F RAME [n]
LEFT
LS B n-1 MSB n
0 63 62
RIGHT
2
S Mode
"Serial Inputs" on page
IDP_PDAP_CTL
ADSP-2126x SHARC Processor Hardware Reference
LSB n MSB n
61 32 31
FRAME [n]
LSB n
3 3
FRAME [n]
LEF T
register. When used in parallel mode,
RIGHT
MS B n
32 3 1
FRAME [n]
RIGHT
11-3, or in a direct
IDP_P-