Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 16

Contents
Clock Signal Options .................................................................. 9-33
Frame Sync Options ................................................................... 9-34
Framed Versus Unframed Frame Syncs ................................... 9-34
Internal Versus External Frame Syncs ..................................... 9-35
Active Low Versus Active High Frame Syncs .......................... 9-36
Sampling Edge for Data and Frame Syncs .............................. 9-36
Early Versus Late Frame Syncs ............................................... 9-37
Data-Independent Frame Sync .............................................. 9-38
Data Word Formats .................................................................... 9-39
Word Length ........................................................................ 9-39
Endian Format ...................................................................... 9-40
Data Packing and Unpacking ................................................ 9-40
Data Type ........................................................................ 9-41
Companding .................................................................... 9-42
SPORT Control Registers and Data Buffers ................................ 9-44
Register Writes and Effect Latency ......................................... 9-50
Serial Port Control Registers (SPCTLx) ................................. 9-50
Transmit and Receive Data Buffers ........................................ 9-60
Clock and Frame Sync Frequencies (DIV) ............................. 9-62
SPORT Interrupts ................................................................ 9-64
Moving Data Between SPORTS and Internal Memory ................ 9-65
DMA Block Transfers ............................................................ 9-66
Setting Up DMA on SPORT Channels ............................. 9-68
xvi ADSP-2126x SHARC Processor Hardware Reference