Setting Computational Modes
40-Bit Floating-Point Format
When in extended-precision mode (
40-bit extended-precision floating-point mode, which has eight additional
LSBs of the mantissa and is compliant with the 754/854 standards. How-
ever, results in this format are more precise than the IEEE single-precision
standard specifies. Extended-precision floating-point data uses a 31-bit
mantissa with a 8-bit exponent plus sign bit.
16-Bit Floating-Point Format (Short Word)
The DSP supports a 16-bit floating-point storage format and provides
instructions that convert the data for 40-bit computations. The 16-bit
floating-point format uses an 11-bit mantissa with a 4-bit exponent plus
sign bit. The 16-bit data goes into bits 23 through 8 of a data register.
Two shifter instructions,
unpacking conversions between 32-bit floating-point words and 16-bit
floating-point words. The
ing-point number in a data register into a 16-bit floating-point number.
converts a 16-bit floating-point number in a data register to a
Funpack
32-bit IEEE floating-point number. Each instruction executes in a single
cycle.
When 16-bit data is written to bits 23 through 8 of a data register, the
DSP automatically extends the data into a 32-bit integer (bits 39 through
8). If the
bit in
SSE
bits. If the
SSE
The 16-bit floating-point format supports gradual underflow. This
method sacrifices precision for dynamic range. When packing a number
that would have underflowed, the exponent clears to zero and the mantissa
(including a "hidden" 1) right-shifts the appropriate amount. The packed
result is a denormal, which can be unpacked into a normal IEEE float-
ing-point number.
2-14
and
Fpack
instruction converts a 32-bit IEEE float-
Fpack
is set (1), the DSP sign extends the upper 16
MODE1
bit is cleared (0), the DSP zeros the upper 16 bits.
ADSP-2126x SHARC Processor Hardware Reference
bit=0), the DSP supports a
RND32
, perform the packing and
Funpack
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