Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 294

IOP/Core Interaction Options
this is the
IDP_DMAx_STAT
even if DMA, through some IDP channel, is not intended.
The following are some other I/O processor interrupt attributes.
• When an unchained (single block) DMA process reaches comple-
tion (as the count decrements to zero) on any DMA channel, the
I/O processor latches that DMA channel's interrupt. It does this by
setting the DMA channel's interrupt latch bit in the
DAI_IRPTL_H
• For chained DMA, the I/O processor generates interrupts in one of
two ways: If
chain; if
chain. (For more information on DMA chaining, see
troller Operation" on page
• When a DMA channel's buffer is not being used for a DMA pro-
cess, the I/O processor can generate an interrupt on single word
writes or reads of the buffer. This interrupt service differs slightly
for each port. For more information on single word inter-
rupt-driven transfers, see
on page
During interrupt-driven DMA, programs use the interrupt mask bits in
the ,
IMASK LIRPTL
isters to selectively mask DMA channel interrupts that the I/O processor
latches into the

The I/O processor only generates a DMA complete interrupt when
the channel's count register decrements to zero as a result of actual
DMA transfers. Writing zero to a count register does not generate
the interrupt. To stop a DMA preemptively, write a one to the
count register. This causes one more word to be transferred or
received and an interrupt is then generated.
7-4
bits of the
, or
DAI_IRPTL_L
= 1, an interrupt occurs for each DMA in the
PCI
= 0, an interrupt occurs at the end of a complete
PCI
"Parallel Port Control Register (PPCTL)"
A-108, and
SPCTL
,
DAI_IRPTL_PRI
, ,
IRPTL LIRPTL DAI_IRPTL_H
ADSP-2126x SHARC Processor Hardware Reference
register can become active
DAI_STAT
registers.
-8).
register in Table 9-6 on page
, , and
DAI_IRPTL_RE
, and
DAI_IRPTL_L
, ,
IRPTL LIRPTL
"DMA Con-
9-51.
reg-
DAI_IRPTL_FE
registers.