Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 556

EXTERNAL
OSCILLATOR
OR XTAL
CLKIN
BUFFER
AMP
SHARC ADSP-2126x
Figure 13-1. Clock Inputs
Note that any clock and frame sync signals generated by the serial ports
are also subject to these jitter problems because the SPORT clock is gener-
ated from the core clock. However, a SPORT can produce data output
while being a clock and frame sync slave. The clock generated by the
SPORT is sufficient for most serial communications, but it is suboptimal
for analog conversion. Therefore, all precision data converters should be
synchronized to a clock generated by the PCG or to a clean (low jitter)
clock that is fed into the SRU off-chip via a pin.

Any clock or frame sync unit should be disabled (have its enable bit
cleared) before changing any of the associated parameters. After
disabling PCG, delay of N core clock cycles (N = PCG source clock
period/CLKIN period) should be provided before programming
PCG with new parameters.
13-2
M/N
CORE
CORE CLOCK
PLL
GENERATOR
PRECISION
SRU
CLOCK
GENERATOR
EXTERNAL
OSCILLATOR
ADSP-2126x SHARC Processor Hardware Reference
CORE CLOCK
CORE
SPORT