Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 841

SPORT4 transmit data buffer,
SPORT5 divisor for transmit/receive See
DIV5 register
SPORT5 receive data buffer,
SPORT5 serial control See SPCTL5
register
SPORT5 transmit data buffer,
SPORT Chain Pointer (CPSPxx) registers,
A-91
SPORT Count (SPCNTx) registers,
SPORT Divisor (DIVx) registers,
SPORT DMA Count (CSPx) registers,
A-91
SPORT DMA Index (IISPx) registers,
A-90
SPORT DMA Modifier (IMSPx) registers,
A-90
SPORT DMA (SDEN), enabling,
SPORT Multichannel Control
(SPMCTLxy) registers,
SPORT operating mode, selected via
SPCTLx register,
SPORT operation modes,
2
I S, 9-18
See OPMODE bit
SPORT operation modes, left-justified
sample pair, 9-14
SPORT operation modes, multichannel,
9-24
SPORT operation modes, standard DSP
serial, 9-11
SPORT Receive Buffer (RXSPx) registers,
A-85
SPORT Receive Compand (MRxCCSy)
registers, A-89
SPORT Receive Select (MRxCSy) registers,
A-88
ADSP-2126x SHARC Processor Hardware Reference
9-48
9-48
9-48
A-87
A-86
9-17
A-79
9-9
9-51
SPORTs
bidirectional functions,
registers, A-69
serial ports, 9-1
SPORT Serial Control (SPCTLx) registers,
9-27, A-69
SPORT Serial Port Control (SPCTLx)
registers, 9-50
SPORT Transmit Buffer (TXSPx)
registers, A-85
SPORT transmit channel 4 (SP4I),
SPORT Transmit Compand (MTxCCSy)
registers, A-88
SPORT Transmit Select (MTxCSy)
registers, A-87
SPORTx divisor for transmit/receive See
DIVx registers
SPORTx_FS pins, 9-6
SPORTx multichannel receive compand
select x See MR1CCSx register
SP registers, A-64
SPTRAN bit, 9-6, 9-56,
SPxI bit, 9-65
SRAM (memory), 1-2
SRAM modes,16-bit vs. 8-bit,
SRDxH/L(secondary registers, DAGs) bits,
4-4
SREG (system) registers,
SRRFH/L (Secondary registers, LO/HI)
bits, 2-41
SRST bit, A-45
SRU, 9-6
bidirectional pin buffers,
connecting peripherals,
connecting through,
connection groups, 12-17
Group A connections,
Group B connections,
Group C connections,
Group D connections,
Index
9-1
A-32
A-78
8-11
A-3
12-12
12-3
12-15
12-18
12-19
12-20
12-21
I-31