Transmission Error Bit (Tunf) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

3. The
MME
4. An SPI interrupt is generated.
These four conditions persist until the
1-to-clear (W1C-type) software operation. Until the
SPI cannot be re-enabled, even as a slave. Hardware prevents the program
from setting either
When is cleared, the interrupt is deactivated. Before attempting to
MME
re-enable the SPI as a master, the state of the
checked to ensure that it is high; otherwise, once
another mode-fault error condition will immediately occur. The state of
the input pin is reflected in the Input Slave Select Status bit (bit 7) in the
register.
SPIFLG
As a result of
SPIEN
drivers ( ,
MOSI MISO
output pins revert to control by the flag I/O module registers. This may
cause contention on the slave-select lines if these lines are still being driven
by the ADSP-2126x. In order to ensure that the slave-select output drivers
are disabled once a
pins as inputs by clearing (= 0) the
the register prior to configuring the SPI port. See the
FLAGS
Register (FLAGS)" on page

Transmission Error Bit (TUNF)

The bit is set in the
TUNF
transmission are met and there is no new data in
In this case, the transmission contents depend on the state of the
in the register. The
SPICTL
operation.
ADSP-2126x SHARC Processor Hardware Reference
status bit in
SPISTAT
or
SPIEN SPIMS
and being cleared, the SPI data and clock pin
SPIMS
, and ) are disabled. However, the slave-select
SPICLK
error occurs, the program must configure these
MME
A-39.
SPISTAT
bit is cleared by a W1C-type software
TUNF
Serial Peripheral Interface Port
is set.
bit is cleared by a write
MME
while is set.
MME
input pin should be
SPIDS
SPIEN
, ,
FLG0O FLG1O FLG2O
register when all of the conditions of
TXSPI
bit is cleared, the
MME
and are set,
SPIMS
, and bits in
FLG3O
"Flag Value
( is empty).
TXSPI
SENDZ
10-41
bit