Secondary Processor Element (Pey) - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

using the Internal Memory Data Width (
ter. If a block's
access 32-bit data. If a block's
to the block access 48-bit data. If a program tries to write 40-bit data (for
example, a data register-to-memory transfer), the transfer truncates the
lower 8 bits from the register; only writing 32 most significant bits.
If a program tries to read 40-bit data (for example, a memory-to-data reg-
ister transfer), the transfer zero-fills the lower 8 bits of the register, only
reading the 32 most significant bits (MSBs).
The Program Memory Bus Exchange (
these transfer rules—all loads and or stores of the
as 48-bit accesses unless forced to a 64-bit access with the
any 40-bit data must be stored in a memory block configured for 32-bit
words, the program uses the
words. Programs should take care not to corrupt any 32-bit data with this
type of access.
Words and 48-Bit Words" on page 5-16.

The Long word (
accesses and overrides all other factors (SIMD,

Secondary Processor Element (PEy)

When the
PEYEN
gle-Instruction, Multiple-Data (SIMD) mode. In SIMD mode, many data
access operations differ from the DSP's default Single-Instruction, Sin-
gle-Data (SISD) mode. These differences relate to doubling the amount of
data transferred for each data access.
Accesses in SIMD mode transfer both an explicit (named) location and an
implicit (unnamed, complementary) location. The explicit transfer is a
data transfer between the explicit register and the explicit address, and the
implicit transfer is between the implicit register and the implicit address.
ADSP-2126x SHARC Processor Hardware Reference
bit is cleared (=0), normal word accesses to the block
IMDWx
IMDWx
register to access the 40-bit data in 48-bit
PX
For more information, see "Restrictions on Mixing 32-Bit
) mnemonic only effects normal word address
LW
bit in the
MODE1
) bits in the
IMDWx
bit is set (=1), normal word accesses
) register is the only exception to
PX
PX
register is set (=1), the DSP is in Sin-
Memory
regis-
SYSCTL
register are performed
mnemonic. If
LW
).
IMDWx
5-19