Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 837

signals
slave select (SPI), 10-49
signed data, 2-15
signed input, 2-30
sign extension, A-6
SIMD mode, 1-6, 1-15, 3-18,
complementary registers,
computational operations,
defined, 2-45
implicit operations, 2-47
status flags, 2-50
SIMD (single-instruction, multiple-data)
mode, A-6
single serial shift register path,
single-step (SS) bit, A-51
single word interrupts,
single word transfers, 9-73
SISD mode, 5-28
defined, 1-6
unidirectional register transfer,
slave
device, 10-6
DMA operations, 10-17
operation, configure for,
slave mode DMA operations (SPI),
slave mode operation, configure for,
SLEN bits, 9-15, 9-21, 9-54,
SLENx bits, 9-54
software interrupt (SFT0x) bit,
software interrupt x, user (SFTxI) bit,
software reset See SRST bit
software reset (SYSRST) bit,
SOVFI (stack overflow/full) bit,
SOVFI (stack overflow interrupt) bit,
SP0I (serial port interrupt) bit,
SP2I (serial port interrupt) bit,
SP4I (serial port interrupt) bit,
SPCNTx registers, A-87
SPCTL2 register, 9-45
SPCTL3 register, 9-45
ADSP-2126x SHARC Processor Hardware Reference
5-28
2-47
2-50
6-2
9-73
2-53
10-10
10-48
10-44
A-76
A-30
A-30
A-51
A-28
3-17
A-32
A-32
A-32
SPCTL4 register, 9-47
SPCTL5 register, 9-47
SPCTLx control bit comparison in four
SPORT operation modes,
SPCTLx control bits for left-justify sample
pair mode, 9-11, 9-20
SPCTLx Control registers,
SPCTLx register bit descriptions,
SPCTLx registers, 7-24, 9-3, 9-6, 9-7,
9-27, 9-48, 9-50, 9-51,
S/PDIF, G-9
SPEN_A bit, 9-15
SPEN_B bit, 9-15
SPEN bit, 9-53, A-76
SPEN_x bits, 9-53
SPI
address, chain pointer,
address, TCB, 10-49
baud rate See SPIBAUD register
baud setup See SPIBAUD register
bits, A-95
block diagram, 10-2
chaining, DMA, 10-46,
clock rate, 10-4
clock signal, 10-4
configuration, changing,
configured as a master,
configuring and enabling,
core transmit and receive operations,
10-12
data fetch See GM bit
device select input pin,
device select signal, 10-6
disable, 10-8
DMA, switching from transmit to receive
mode, 10-50
DMA registers, A-103
DMA transfers, 10-12
eight-bit word lengths,
enable, 10-8
Index
9-51
9-33
A-76
A-69
10-46
10-48
10-20
10-9
10-45
10-37
10-30
I-27