Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 176

Summary
Table 3-24. Sequencer Registers Read and Effect Latencies
Register Contents
FADDR
DADDR
PC
PCSTK
PCSTKP
LADDER
CURLCNTR
LCNTR
Table 3-25. System Registers Read and Effect Latencies
Register
MODE1
MODE2
IRPTL
IMASK
IMASKP
MMASK
FLAGS
LIRPTL
ASTATX
ASTATY
STKYX
3-64
Fetch address
Decode address
Execute address
Top of PC stack
PC stack pointer
Top of loop address stack
Top of loop count stack (current loop
count)
Loop count for next DO UNTIL loop 32
Contents
Mode control bits
Mode control bits
Interrupt latch
Interrupt mask
Interrupt mask pointer (for nesting) 32
Mode mask
Flag inputs
Interrupt latch/mask
Arithmetic status flags
Arithmetic status flags
Sticky status flags
ADSP-2126x SHARC Processor Hardware Reference
Bits Read
Latency
24 —
24 —
24 —
24 0
5 1
32 0
32 0
0
Bits Read
Latency
32 0
32 0
32 0
32 0
1
32 0
32 0
32 0
32 0
32 0
32 0
Effect
Latency
—
—
—
0
1
0
0
0
Maximum
Effect
1
Latency
1
1
1
1
1
1
1
1
1
1
1