Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 507

•
IDP_Pxx_PDAPMASK
ify the input mask, if the PDAP is used.
•
IDP_PORT_SELECT
ify input from the DAI pins or the Parallel Port pins, if the
PDAP is used.
•
IDP_PDAP_CLKEDGE
to specify if data is latched on the rising or falling clock
edge, if the PDAP is used.
3. Keep the clock and frame sync inputs of all serial inputs and/or
PDAP connected to
and
SRU_FS2
4. Connect all of the inputs to the IDP by writing to the
SRU_DAT4
Connect the clock and frame sync of any unused ports to
5. Set the desired value for N_SET variable (the
in the
IDP_CTL
6. Set the
to
HIGH
to to unmask the interrupt. Set bit 8 of the
LOW
ister (
IDP_FIFO_GTN_INT
low priority core interrupt when the number of words in the FIFO
is greater than the value of N set in step 5.
7. Enable the PDAP by setting
DAP_CTL
8. Enable the IDP by setting
register).

Do not set the
ADSP-2126x SHARC Processor Hardware Reference
bits in the
. Use the
LOW
registers to specify these inputs.
, ,
SRU_FS1 SRU_FS2
register).
IDP_FIFO_GTN_INT
and set the corresponding bit in the
) as needed to generate a high priority or
register), if required.
IDP_DMA_EN
bits in the
IDP_PDAP_CTL
IDP_PDAP_CTL
bit (bit 29) in the
,
SRU_CLK1
, and
SRU_CLK1 SRU_CLK2
bit (bit 8 of the
DAI_IRPTL_RE
(bit 31 in the
IDP_PDAP_EN
bit (bit 7 in the
IDP_ENABLE
bit (bit 5 of the
IDP_CTL
Input Data Port
register to spec-
register to spec-
register
IDP_PDAP_CTL
,
SRU_CLK2 SRU_FS1
SRU_DAT3
registers.
.
LOW
bits, 3–0,
IDP_NSET
register)
register
DAI_IRPTL_FE
DAI_IRPTL_PRI
IDP_P-
IDP_CTL
register).
11-17
,
,
reg-