Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 727

Table A-30. SPIDMAC Register Bits
Bit(s) Name
0 SPIDEN
1 SPIRCV
2 INTEN
3 Reserved
4 SPICHEN
6:5 Reserved
7 FIFOFLSH
8 INTERR
9 SPIOVF
10 SPIUNF
ADSP-2126x SHARC Processor Hardware Reference
Function
DMA Enable. Enables if set (= 1) or dis-
ables if cleared (= 0) DMA for the SPI
port.
DMA Direction. When set, the IOP emp-
ties the RXSPI buffer, when cleared, the
IOP fills the TXSPI buffer.
0 = SPI Transmit DMA (Memory read)
1 = SPI Receive DMA (Memory write)
Enable DMA Interrupt. Enables if set
(= 1) or disables if cleared (= 0) an inter-
rupt upon completion of the DMA trans-
fer.
SPI DMA Chaining Enable. Enables if set
(=1) or disables if cleared (= 0) DMA
chaining.
DMA FIFO Flush. Clears the four-deep
FIFO and FIFO status bits if set (= 1).
Once a one is written to this bit, it remains
set. A zero need to be written to clear this
bit.
Enable Interrupt on Error. Enables if set
(= 1) or disables if cleared (= 0) an inter-
rupt when an error in the transmission
occurs.
Receive Overflow Error (SPIRCV=1). Set
when SPIRCV = 1 and data is received
with the receive buffer full (1 = error data
received with receive data buffer RXSPI
full in receive mode DMA).
SPI Transmit Underrun Error. Set when
SPIRCV = 0 and the SPI transmits without
any new data in the transmit buffer TXSPI.
Registers Reference
Type Default
Control 0
Control 0
Control 0
Control 0
Control 0
Control 0
Status 0
Status 0
A-105