Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 159

When a program enables the timer, the timer starts decrementing the
register at the end of the next clock cycle. If the timer is subse-
TCOUNT
quently disabled, the timer stops decrementing
cycle as shown in
TIMER
ENABLE
CCLK
TIMER
DISABLE
CCLK
Figure 3-5. Timer Enable and Disable
The timer expired event (
rupts, and
TMZHI
interrupts to select timer expired priority, see
page 3-55.
As with other interrupts, the sequencer needs two cycles to fetch and
decode the first instruction of the timer expired service routine before exe-
cuting the routine. The pipeline execution for the timer interrupt appears
in Figure 3-23 on page
Programs can read and write the
universal register transfers. Reading the registers does not effect the timer.
Note that an explicit write to
ADSP-2126x SHARC Processor Hardware Reference
Figure 3-5.
Set TIMEN
in MODE2
TCOUNT=N TCOUNT=N
Clear TIMEN
Timer Inactive
in MODE2
TCOUNT=M–1TCOUNT=M–2 TCOUNT=M–2
decrements to zero) generates two inter-
TCOUNT
. For information on latching and masking these
TMZLI
3-51.
TPERIOD
TCOUNT
Program Sequencer
TCOUNT
Timer Active
TCOUNT=N-1
"Latching Interrupts" on
and registers by using
TCOUNT
takes priority over the sequencer's
after the next clock
3-47