#define FSR
#define ICLK
/* Default Buffer Length */
#define BUFSIZE 10
.SECTION/DM seg_dmda;
/*Transmit buffer*/
.var tx_buf5a[BUFSIZE] = 0x11111111,
/*Receive buffer*/
.var rx_buf4a[BUFSIZE];
/* Main code section */
.global _main;
.SECTION/PM seg_pmco;
_main:
/* SPORT Loopback: Use SPORT4 as RX & SPORT5 as TX.
For no loopback (TDM mode), program MTaCSb
[a=0,2,4 & b=0,1,2,3] and MRcCSd [a=1,3,5 & b=0,1,2,3], */
/* initially clear SPORT control register */
r0 = 0x00000000;
dm(SPCTL4) = r0;
ADSP-2126x SHARC Processor Hardware Reference
0x00002000
0x00000400
0x22222222,
0x33333333,
0x44444444,
0x55555555,
0x66666666,
0x77777777,
0x88888888,
0x99999999,
0xAAAAAAAA;
Serial Ports
9-83
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