32-Bit Spi Host Boot - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Booting
processor expects to receive instructions and data packed in a least signifi-
cant word (LSW) format.
Figure 15-8 shows how a pair of instructions are packed for SPI booting
using a 32-, 16-, and an 8-bit device. These two instructions are received
as three 32-bit words as illustrated in
33445566
32-BIT HOST
5566
16-BIT HOST
8-BIT HOST 66 55
t = 0
Figure 15-8. Instruction Packing for Different Hosts
The following sections examine how data is packed into internal memory
during SPI booting for SPI devices with widths of 32, 16, or 8 bits.

32-bit SPI Host Boot

Figure 15-9 shows 32-bit SPI host packing of 48-bit instructions executed
at PM addresses 0x80000 and 0x80001. The 32-bit word is shifted to
internal program memory during the 256-word kernel load.
The following example shows a 48-bit instructions executed:
[0x80000] 0x112233445566
[0x80001] 0x7788AABBCCDD
15-24
WORDS
CCDD1122
3344 1122 CCDD
44 33 22 11 DD CC
ADSP-2126x SHARC Processor Hardware Reference
Figure 15-7.
7788AABB
AABB 7788
[0x80001] 0x7788 AABBCCDD
BB AA 88 77
t = 96 SPICLK
INSTRUCTIONS IN
INTERNAL MEMORY
[0x80000] 0x1122 33445566