79
63
MRF2
MRF1
OVERFLOW
FRACTIONAL RESULT
OVERFLOW
OVERFLOW
Figure 2-8. Multiplier Fixed-Point Result Placement
The
register is divided into
MRF
be individually read from or written to the register file. Each of these reg-
isters has the same format. When data is read from
sign-extended to 32 bits as shown in
eight LSBs of the 40-bit register file location when data is read from
, or
to the register file. When the DSP writes data into
MRF1
MRF0
, or
from the 32 MSBs of a register file location, the eight LSBs
MRF1
MRF0
are ignored. Data written to
MSB of
in the 16 bits of
MRF1
sign-extended.
16 BITS
16 BI TS
MRF2
S IGN-EXTEND
Figure 2-9. MR Transfer Formats
ADSP-2126x SHARC Processor Hardware Reference
31
0
MRF0
UNDERFLOW
INTEGER RESULT
,
MRF2
Figure
is sign-extended to
MRF1
. Data written to
MRF2
8 BITS
ZE ROS
32 BITS
MRF1
Processing Elements
, and
registers, which can
MRF1
MRF0
MRF2
2-9. The DSP zero-fills the
MRF2
MRF0
8 BI TS
ZEROS
32 BI TS
MRF0
, it is
,
MRF2
,
MRF2
, repeating the
is not
8 BITS
ZEROS
2-25
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