Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 699

Table A-23. SPCTLx Register Bit Descriptions (Cont'd)
Bits Name
12 CKRE
13 FSR
14 IFS
(IMFS)
15 DIFS
16 LFS
(LMFS, FRFS)
17 LAFS
18 SDEN_A
19 SCHEN_A
20 SDEN_B
21 SCHEN_B
ADSP-2126x SHARC Processor Hardware Reference
Definition
Clock Rising Edge Select. Selects whether the serial port uses the ris-
ing edge if set, (= 1) or falling edge if cleared, (= 0) of the clock sig-
nal to sample data and the frame sync. CKRE is reserved when the
2
SPORT is in I S and Left-justified Sample Pair mode.
Frame Sync Required Select. Selects whether the serial port requires
if set, (= 1) or does not require if cleared, (= 0) a transfer frame sync.
FSR is reserved when the SPORT is in I
ple Pair mode and multichannel mode.
Internal Frame Sync Select. Selects whether the serial port uses an
internally generated frame sync if set, (= 1) or uses an external frame
sync if cleared, (= 0). This bit is reserved when the SPORT is in I
Left-justified Sample Pair mode and Multichannel mode.
Data Independent Frame Sync Select. Selects whether the serial port
uses a data-independent frame sync (sync at selected interval,
if set, = 1) or uses a data-dependent frame sync (sync when TX FIFO
is not empty or when RX FIFO is not full). This bit is reserved when
the SPORT is in Multichannel mode.
Active Low Frame Sync Select. Selects an active low FS if set, (= 1)
or active high FS if cleared, (= 0).
Late Transmit Frame Sync Select. Selects a late frame sync (FS
during first bit, if set, = 1) or an early frame sync (FS before first bit,
if cleared, = 0). This bit is reserved when the SPORT is in multi-
channel mode.
Enable Channel A Serial Port DMA. Enables if set, (= 1) or disables
if cleared, (= 0) the serial port's A channel DMA.
Enable Channel A Serial Port DMA Chaining. Enables if set, (= 1)
or disables if cleared, (= 0) the serial port's channel A DMA chaining.
Enable Channel B Serial Port DMA. Enables if set, (= 1) or disables
if cleared, (= 0) the serial port's channel B DMA.
Enable Channel B Serial Port DMA Chaining. Enables if set, (= 1)
or disables if cleared, (= 0) the serial port's channel B DMA chaining.
Registers Reference
2
S mode, Left-Justified Sam-
2
S,
A-77