Instruction Pipeline - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Instruction Pipeline

Instruction Pipeline
The program sequencer determines the next instruction address by exam-
ining both the current instruction being executed and the current state of
the processor. If no conditions require otherwise, the DSP fetches and exe-
cutes instructions from memory in sequential order.
To achieve a high execution rate while maintaining a simple programming
mode, the DSP employs a three stage pipeline to process instructions:
1. Fetch cycle. The DSP reads the instruction from either the on-chip
memory or the instruction cache.
2. Decode cycle. The DSP decodes the instruction, generating condi-
tions that control instruction execution and program flow.
3. Execute cycle. The DSP executes the instruction; the operations
specified by the instruction complete in a single cycle.
In a sequential program flow, when one instruction is being executed, the
next instruction is being decoded, and the instruction following that is
being fetched. Sequential program flow usually has a throughput of one
instruction per cycle. In the event of cache misses, instructions may take
more than one cycle.
Figure 3-2 illustrates how the instructions starting at address 0x08 are
processed by the pipeline. While the instruction at address 0x08 is being
executed, the instruction 0x09 is being decoded and the instruction at
address 0xA is being fetched.
While sequential execution takes one core clock cycle per instruction,
branching (nonsequential executions) can temporarily reduce this rate.
Nonsequential program operations include:
• Program memory data accesses that conflict with instruction
fetches
3-4 ADSP-2126x SHARC Processor Hardware Reference