Circular Buffering Mode; Broadcast Loading Mode - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Circular Buffering Mode

The bit in the
CBUFEN
where the DAG supplies addresses that range within a constrained buffer
length (set with an
with a register), and increment addresses on each access by a modify
B
value (set with an

The circular buffer enable bit (
cleared (= 0) at reset. This makes the ADSP-2126x processor code
incompatible with the ADSP-2106x SHARC family
(ADSP-21060/1/2 and ADSP-21065L) where circular buffering is
active upon reset. For code compatibility, programs ported to the
ADSP-2126x processors should include the instruction:
BIT SET MODE1 CBUFEN
For more information on setting up and using circular buffers, see
"Addressing Circular Buffers" on page
the DAGs can generate an interrupt on buffer overflow (wraparound). For
more information, see

Broadcast Loading Mode

The and
BDCST1
An example of broadcast loading is when a program uses one load com-
mand to load multiple registers. When the
performs a dual data register load on instructions that use the
for the address. The DAG loads both the named register (explicit register)
in one processing element and loads that register's complementary register
(implicit register) in the other processing element. The
register enables this feature for the
MODE1
Enabling either DAG register to perform a broadcast load has no effect on
register stores or loads to universal registers (
the register file data registers.
ADSP-2126x SHARC Processor Hardware Reference
register enables circular buffering—a mode
MODE1
register). Circular buffers start at a base address (set
L
register).
M
.
"Using DAG Status" on page
bits in the
BDCST9 MODE1
Table 4-1
Data Address Generators
) in the
CBUFEN MODE1
4-12. When using circular buffers,
4-9.
register enable broadcast loading.
bit is set (=1), the DAG
BDCST1
BDCST9
register.
I9
). The one exception is
Uregs
demonstrates the effects of a
register is
register
I1
bit in the
4-5