Parallel Port Pins - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Parallel Port Pins

This section describes the pins that the parallel port uses for its operation.
For a complete list of pin descriptions and package pinouts, see the prod-
uct-specific data sheet for your device.
• Address/Data (AD15–0) pins. The ADSP-2126x processor pro-
vides time multiplexed address/data pins that are used for
providing both address and data information. The state of the
address/data pins is determined by the 8- or 16-bit operating mode
and the state of the
• Read strobe (
read operation. Data is latched into the processor using the rising
edge of this signal.
• Write strobe (
write operation. The rising edge of this signal can be used by mem-
ory devices to latch the data from the processor.
• Address Latch Enable (ALE) pin. The address latch enable pin is
used to strobe an external latch connected to the address/data pins
(
AD15–0
of the external memory address. An
first access after the parallel port is enabled and anytime the upper
16 bits of the address change from a previous cycle.
In 8-bit mode, a maximum of 24 bits of external address are facilitated
through latching the upper 16 bits,
latch during the
are provided through
EA7–0
when the or
RD
In 16-bit mode, a maximum of 16 bits of external address are facilitated
through latching the upper 16 bits of
nal latch during the
ADSP-2126x SHARC Processor Hardware Reference
,
ALE RD
) pin. This output pin is asserted low to indicate a
RD
) pin. This output pin is asserted low to indicate a
WR
). The external latch holds the most significant bits (MSBs)
phase of the cycle. The remaining 8 bits of address
ALE
AD15–8
signal is asserted.
WR
phase of the cycle. The
ALE
, and pins.
WR
cycle is inserted for the
ALE
, from
EA23–8 AD15–0
during the second half of the cycle
from
AD15–0 AD15–0
AD15–0
Parallel Port
into the external
into the exter-
represent the
8-3