Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 667

Table A-15. SYSCTL Register Bit Descriptions
Bits Name
0 SRST
1 Reserved
2 IIVT
6–3 Reserved
7 DCPR
8 Reserved
9 IMDW0
10 IMDW1
15–11 Reserved
16 IRQ0EN
17 IRQ1EN
18 IRQ2EN
19 TMREXPEN
ADSP-2126x SHARC Processor Hardware Reference
Definition
Software Reset. Resets (when set, = 1) the processor. When a
program sets (= 1) SRST, the processor responds to the non-mas-
kable RSTI interrupt and clears (= 0) SRST.
Internal Interrupt Vector Table. Forces placement of the inter-
rupt vector table at address 0x0008 0000 regardless of booting
mode (if 1) or allows placement of the interrupt vector table as
selected by the booting mode (if 0).
DMA Channel Priority Rotation Enable. Enables (rotates if set,
= 1) or disables (fixed if cleared, = 0) priority rotation among
DMA channels. Permits core writes.
Internal Memory Data Width 0. Selects the data access size for
internal memory as 48-bit data if set, (= 1) or 32-bit data if
cleared, (= 0). Permits core writes.
Internal Memory Data Width 1. Selects the data access size for
internal memory as 48-bit data if set, (= 1) or 32-bit data if
cleared, (= 0). Permits core writes.
Flag0 Interrupt Mode.
1 = Flag0 pin is allocated to interrupt request
0 = Flag0 pin is a general purpose I/O pin. Permits core writes.
Flag1 Interrupt Mode.
1 = Flag1 pin is allocated to interrupt request
0 = Flag1 pin is a general purpose I/O pin. Permits core writes.
Flag2 Interrupt Mode.
1 = Flag2 pin is allocated to interrupt request
0 = Flag2 pin is a general purpose I/O pin. Permits core writes.
Flag Timer Expired Mode. Read/Write
1 = Flag3 pin outputs are timer-expired signal (TIMEXP).
0 = Flag3 pin is a general purpose I/O pin.
Permits core writes.
Registers Reference
.
IRQ0
.
IRQ1
.
IRQ2
A-45