Analog Devices ADSP-21261 SHARC Hardware Reference Manual page 429

/* Next TCB location for tx_tcb1 is tx_tcb2 */
/* Mask the first 19 bits of the TCB location */
r0 = (tx_tcb2 + 3) & 0x7FFFF;
dm(tx_tcb1) = r0;
/* Initialize SPORT DMA transfer by writing to the CP reg */
dm(CPSP1A) = r0;
_main.end: jump (pc,0);
Listing 9-2. SPORT Transmit Using Direct Core Access
/* SPORT Control Registers */
#define TXSP2A
#define RXSP3A
#define DIV2
#define DIV3
#define SPCTL2
#define SPCTL3
#define SPMCTL23 0x404
/* SPMCTL Bits */
#define SPL
/* SPCTL Bits */
#define SPEN_A
#define SDEN_A
#define SLEN32
#define SPTRAN
#define IFS
#define FSR
#define ICLK
/* Default Buffer Length */
ADSP-2126x SHARC Processor Hardware Reference
0x460
0x465
0x402
0x403
0x400
0x401
0x00001000
0x00000001
0x00040000
0x000001F0
0x02000000
0x00004000
0x00002000
0x00000400
Serial Ports
9-79